Focal plane arrays (FPAs), based on their imaging capabilities can be utilized for a wide range of applications, ranging from medical diagnostics to military defense and to environmental monitoring. The development of a new generation of FPAs is primarily hindered upon their effective design and fabrication. A typical FPA is primarily composed of an array of pixels with a bottom electrical contact, a photodetector, and a top electrical contact. The bottom contact is formed on the bottom side of each pixel in the array. The top contact is defined at the base of the pixel array along its boundary. The top contact makes electrical contact to the pixel array through a common, relatively thick semiconductor ground plane. A completed FPA is bonded to a read-out integrated circuit (ROIC) with conductive bonding pads and epoxy.
During the fabrication process, each FPA requires a substrate removal step to effectively allow reception of incoming radiation to the pixel array. With such a FPA architecture as discussed above, substrate removal is performed on a single FPA at the die level, making the process slow and expensive to perform. Also, the option for additional chip processing after substrate removal is not easily possible. Backside patterning is also performed one die at a time. Further, excess epoxy in bonding to the ROIC can prevent use of contact photolithography techniques after substrate removal.
In addition to typical FPA fabrication methods using single die processing, the ROIC is susceptible to damage during substrate removal, which can reduce device yield and increase fabrication costs. Also, a thick semiconductor ground plane used in conventional FPAs leads to radiation lost in the doped semiconductor contact layers leading to poor absorption efficiency. Further, the doped semiconductor layer often cracks when the FPA is cycled between room and cryogenic temperatures for image acquisition, which significantly limits the lifetime of the imaging system. Furthermore, additional chip processing after substrate removal is inefficient. Patterning a high resolution structure, such as a frequency selective surface, is inefficient due to existing structures that interfere during photolithography.